The invention relates to flexible instruction execution in a processor pipeline.
A processor pipeline includes multiple stages through which instructions advance, a cycle at a time. An instruction is fetched (e.g., in an instruction fetch (IF) stage or stages). An instruction is decoded (e.g., in an instruction decode (ID) stage or stages) to determine an operation and one or more operands. Alternatively, in some pipelines, the instruction fetch and instruction decode stages could overlap. An instruction has its operands fetched (e.g., in an operand fetch (OF) stage or stages). An instruction issues, which typically starts progression of the instruction through one or more stages of execution. Execution may involve applying the instruction's operation to its operand(s) for an arithmetic logic unit (ALU) instruction, or may involve storing or loading to or from a memory address for a memory instruction. Finally, an instruction is committed, which may involve storing a result (e.g., in a write back (WB) stage or stages).
In a scalar processor, instructions proceed one-by-one through the pipeline, typically in-order according to a program (i.e., in program order), with at most a single instruction being committed per cycle. In a superscalar processor, multiple instructions may proceed through the same pipeline stage at the same time, allowing more than one instruction to issue per cycle, depending on certain conditions (called ‘hazards’), up to an ‘issue width’. Some superscalar processors issue instructions in-order, with consecutive instructions proceeding through the pipeline in program order. Some superscalar processors allow instructions to be reordered and issued out-of-order, which potentially increases overall pipeline throughput. If reordering is allowed, instructions can be reordered within a sliding ‘instruction window’ (whose size can be larger than the issue width), and at the end of the pipeline, a reorder buffer can be used to temporarily store results (and other information) associated with instructions in the instruction window to enable the instructions to be committed in-order (potentially allowing multiple instructions to be committed in the same cycle as long as they are contiguous in the program order).